Phase locked loops, also called PLL circuits, are used in many technical fields of application. Inter alia, they are used for frequency multiplication, frequency division and as frequency synthesizers.
FIG. 1 shows a schematic illustration of the design of an ordinary PLL. This comprises a phase/frequency detector PFD which compares a reference frequency signal fref with a frequency signal fout/N, which is obtained by an N-fold frequency divider N_DIV from the output signal fout from a voltage-controlled oscillator VCO, for phase and frequency differences. The phase/frequency detector PFD outputs switching signals INCR and DECR which are characteristic of the phase and frequency difference between fref and fout/N. These switching signals INCR, DECR are supplied to a charge pump CP which charges and discharges a loop filter CL and thereby prescribes the voltage V0 at the input of the voltage-controlled oscillator VCO.
In the steady state, fout=N·fref, and the two signals fref and fout/N are in phase with one another.
The notional design of the charge pump CP, which is shown in FIG. 1, is known. The charge pump CP comprises two switched constant current sources 1, 2 that are arranged in series between VDD and VSS. The constant current source 1 produces a current Iup, and the constant current source 2 produces a current Idown. The constant current source 1 can be connected to the loop filter CL by means of a switch S1, and charges the loop filter when the switch is in the closed position. Correspondingly, the constant current source 2 (current sink) can be connected to the loop filter CL by means of a switch S2, and the loop filter CL is discharged with the current Idown when S2 is in the closed position and S1 is in the open position. The output current from the charge pump CP, which current charges/discharges the loop filter CL, is thus formed by the difference between the two switched currents Iup and Idown. The switches S1, S2 are in the form of MOS control transistors that are actuated by the switching signals INCR and DECR.
The switching signals INCR and DECR are binary signals. For the period in which the switching signal INCR (DECR) assumes the logic value 1 (“high”), the loop filter CL is charged with the current Iup (discharged with the current Idown). The charge pump CP thus takes pulses of the switching signals INCR and DECR and produces proportional current pulses Iup and Idown.
For the performance of a PLL, it is crucial for the current pulses to be produced with a high level of accuracy. The currents Iup and Idown are intended to be of the same magnitude. This is not always the case in practice, however. The reasons for this are: a mismatch in the speed of p-channel and n-channel transistors in the current sources, a mismatch in the drain/source voltages UDS of p-channel and n-channel transistors in the current sources, and differences in the current sources 1, 2 in the charge pump CP when p-channel and n-channel switching transistors S1, S2 are actuated in the same way.
In the steady state of the PLL, the following applies:∫(Iup−Idown)dt=0.  (1)
If the currents Iup and Idown have different absolute values, it is necessary to compensate for this in the control loop operation in line with equation (1) through different duty cycles for the switching signals INCR and DECR. This is detrimental to the control accuracy of the PLL and causes systematic control jitter to occur.
The specification U.S. Pat. No. 6,611,160 describes a differential charge pump that comprises two charge pump circuits. The charge pump has complementary transistors that insulate the charge pump from switching noise that occurs in the switching transistors.